Z32F0641MCU Datasheet, PDF (44/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
CMR Clock Monitoring Register
To monitor the internal clock and external oscillator, the MCLKMNT/EOSCMNT bits must be set before the
MCLK and EOSC bits are valid. The Clock Monitoring Register is a 16-bit register.
Note: The EOSC bit only checks for the EOSC oscillation, not its stability. When the system detects an
MCLKFAIL interrupt, the MCLKREC bit determines if the system dies or will auto-recover using the ROSC.
The system usually auto-recovers so that it can continue running.
CMR=0x4000_0048
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
R
RW RW RC1 RC1 RW RW RC1 RC1
15 MCLKREC
7
MCLKMNT
6
MCLKIE
5
MCLKFAIL
4
MCLKSTS
3
EOSCMNT
2
EOSCIE
1
EOSCFAIL
0
EOSCSTS
MCLK fail auto recovery
0 MCLK is changed to RINGOSC by default when
MCLKFAIL issued
1 MCLK auto recovery is disabled
MCLK monitoring enable
0 MCLK monitoring disabled
1 MCLK monitoring enabled
MCLK fail interrupt enable
0 MCLK fail interrupt disabled
1 MCLK fail interrupt enabled
MCLK fail interrupt
0 MCLK fail interrupt not occurred
1 Read : MCLK fail interrupt is pending
Write : Clear pending interrupt
MCLK clock status
0 No clock is present on MCLK
1 Clock is present on MCLK
External oscillator monitoring enable
0 External oscillator monitoring disabled
1 External oscillator monitoring enabled
External oscillator fail interrupt enable
0 External oscillator fail interrupt disabled
1 External oscillator fail interrupt enabled
External oscillator fail interrupt
0 External oscillator fail interrupt not occurred
1 Read : External oscillator fail interrupt is pending
Write : Clear pending interrupt
External oscillator status
0 Not oscillate
1 External oscillator is working normally
The clock monitoring function cannot cover all malfunction cases and is only used for reference. Figure 4.9
shows the operational diagram for clock monitoring function.
PS034404-0417
PRELIMINARY
41