Z32F0641MCU Datasheet, PDF (185/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
12-Bit A/D Converter
ADn.MR ADCn Mode Register
The ADC Mode registers are 32-bit registers.
This register configures ADC Operation Mode. This register configures the ADC Operation Mode and should
be written first before the other ADC registers are written.
AD0.MR=0x4000_B000, AD1.MR=0x4000_B100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0 0x0
0x0
RW RW
RW
0x0 0x0 0x0 0x0
0x0
RW RW RW RW
RW
17 DMAEN
DMA enable bit – should be set to ‘1’ when ADCEN=’1’.
When DMA function is enabled, DMA request at every end of
conversion (also in sequential mode) and interrupt request only be
generated when ADC receives DMA done from DMAC.
16 DMACH
DMA channel option
When DMACH is set, Channel information of DMA data will be located
at ADn.DDR[3:0] for half word size transfer.
Channel information is at ADn.DDR [19:16] in default.(DMACH is low)
15 STSEL
Sampling Time Selection
12
ADC Sample & Hold circuit sampling time become (2 + STSEL[3:0])
MCLK cycles
Minimum sampling time is 2 MCLK cycles
10 SEQCNT Number of coversion in a sequence
8
If ADMOD is 2’h0 and SEQCNT is not 3’h0, CSEQN will be increased
up to SEQCNT by trigger event.
000 Single mode
100 5
sequence
AD
conversion
001 2
sequence
AD 101 6
sequence
AD
conversion
conversion
010 3
sequence
AD 110 7
sequence
AD
conversion
conversion
011 4
sequence
AD 111 8
sequence
AD
conversion
conversion
7
ADEN
0
ADC disable
1
ADC enable
6
ARST
0
Stop at the end of sequence.
Should set ASTART as 1 to restart again
1
Restart at the end of sequence.
5
ADMOD
00
Single conversion mode
4
01
Burst conversion mode
10
Reserved
11
Reserved
1
TRGSEL 00
Event Trigger Disabled/Soft-Trigger Only
0
01
Timer Event Trigger
10
MPWM0 Event Trigger
11
Reserved
PS034404-0417
PRELIMINARY
182