Z32F0641MCU Datasheet, PDF (64/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Port Control Unit
PCD.MR PORT D Pin MUX Register
This register is the PD Port Mode select register, and must be set up correctly before using the port to ensure
that the port functions as designed.
PCD.MR=0x4000_1300
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Port
PD0
PD1
PD2
PD3
00
PD0*
PD1*
PD2*
PD3*
Selection Bit
01
10
11
SS0
T8IO
SCK0
T9IO
MOSI0
SCL0
MISO0
SDA0
PCn.CR PORT n Pin Control Register (Except for PCCR)
This register controls the input or output of each port pin. Each pin can be configured as input pin, output pin,
or open-drain pin.
PCA.CR=0x4000_1004, PCB.CR=0x4000_1104, PCD.CR=0x4000_1304
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15 P14 P13 P12 P11 P10 P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Pn
Port control
00 Push-pull output
01 Open-drain output
10 Input
11 Analog
PS034404-0417
PRELIMINARY
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