Z32F0641MCU Datasheet, PDF (24/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PCLK Clock Domain
PCLK is the master clock of all the peripherals. It can be stopped in Power-Down Mode. Each peripheral clock
is generated by the PCER register set.
Clock Configuration
After power up, the default system clock is fed by the RINGOSC (1 MHz) clock. RINGOSC is enabled by
default at power up. The other clock sources are enabled by user controls with the RINGOSC system clock.
The MOSC clock can be enabled by the CSCR register. Before enabling the MOSC block, the pin mux
configuration should be set for XIN, XOUT function. PC12 and PC13 pins are shared with MOSC’s XIN and
XOUT function - PCCMR and PCCCR registers should be correctly configured. After enabling the MOSC
block, you must wait for more than 1 msec to ensure stable operation of crystal oscillation.
The PLL clock can be enabled by the PLLCON register. After enabling the PLL block, you must wait for the
PLL lock flag. When the PLL output clock is stable; you can select MCLK for your system requirement. Before
changing the system clock, Flash access wait should be set to the maximum value. After the system clock is
changed, you will need to set the desired Flash access wait time.
An example flow chart outlining the steps to configure the system clock is shown in Figure 4.5.
Power up
MCLK == RING OSC
(default set)
Set Flash wait control in
FM.CFG.WAIT == Maximum wait
Set MOSC
PCCMR[27:24]←XIN,XOUT
PCCCR[27:24]←analog
CSCR.EOSCCON[1] = 1
N
check EOSCSTS bit in CMR
Y
Wait 5msec for MOSC crystal
oscillation stabilizing
Change MCLK from
RINGOSC to MOSC in SCCR
(MCLK == MOSC)
Set PLL CON
N
Check PLL LOCK bit
in PLLCON
Y
Change MCLK
from MOSC to PLL in SCCR
(MCLK == PLL)
Set flash wait control in
FM.CFG.WAIT
END
Figure 4.5. Clock Configuration Flow Chart
When you speed up the system clock up to maximum operating frequency, you should check the Flash wait
control configuration. Flash read access time is one of the limiting factors in performance. The wait control
recommendation is provided in Table 4.2.
PS034404-0417
PRELIMINARY
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