Z32F0641MCU Datasheet, PDF (127/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Serial Peripheral Interface
13. Serial Peripheral Interface
Overview
One-channel serial Interface is provided for synchronous serial communications with external peripherals. The
Serial Peripheral Interface (SPI) block supports both master and slave modes. Four signals are used for SPI
communication – SS, SCK, MOSI, and MISO.
 Master or Slave operation.
 Programmable clock polarity and phase.
 8, 9, 16, 17-bit wide transmit/receive register.
 8, 9, 16, 17-bit wide data frame.
 Loop-back mode.
 Programmable start, burst, and stop delay time.
 DMA transfer operation.
Figure 13.1 SPI Block Diagram
PS034404-0417
PRELIMINARY
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