Z32F0641MCU Datasheet, PDF (118/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
UART
Un.LCR UART Line Control Register
The UART Line Control Register is an 8-bit register.
U0.LCR=0x4000_800C, U1.LCR=0x4000_810C
7
6
5
4
3
2
1
0
BREAK
STICKP
PARITY
PEN
STOPBIT
DLEN
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
6
BREAK
When this bit is set, TxD pin will be driven at low state in orde
r to notice the alert to the receiver.
0
Normal transfer mode
1
Break transmit mode
5
STICKP
Force parity and it will be effective when PEN bit is set.
0
Parity stuck is disabled
1
Parity stuck is enabled and parity always the bit of PARI
TY.
4
PARITY
Parity mode selection bit and stuck parity select bit
0
Odd parity mode
1
Even parity mode
3
PEN
Parity bit transfer enable
0
The parity bit disabled
1
The parity bit enabled
2
STOPBIT The number of stop bit followed by data bits.
0
1 stop bit
1
1.5 / 2 stop bit
In case of 5 bit data case, 1.5 stop bit is added. In cas
e of 6,7 or 8 bit data, 2 stop bit is added
1
DLEN
The data length in one transfer word.
0
00 5 bit data
01 6 bit data
10 7 bit data
11 8 bit data
Parity bit is generated according to bit 3, 4, 5 of UnLCR register. The following table shows the variation of
parity bit generation.
STICKP PARITY
X
X
PEN
0
Parity
No Parity
0
0
1
Odd Parity
0
1
1
Even Parity
1
0
1
Force parity as “1”
1
1
1
Force parity as “0”
PS034404-0417
PRELIMINARY
115