Z32F0641MCU Datasheet, PDF (47/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
COR
Clock Output Register
The Z32F0641 MCU can drive the clock from internal MCLK clock with a dedicated post divider. The Clock
Output Register is an 8-bit register.
7
6
5
4
3
-
CLKOEN
000
0
R
RW
2
1
CLKODIV
1111
RW
COR=0x4000_0050
0
4
CLKOEN
3
CLKODIV
0
Clock output enable
0 CLKO is disabled and stay “L” output
1 CLKO Is enabled
Clock output divider value
CLKO = MCLK (CLKODIV = 0)
𝑴𝑪𝑳𝑲
𝐂𝐋𝐊𝐎 = _{𝟐 ∗ (𝐂𝐋𝐊𝐎𝐃𝐈𝐕 + 𝟏)} (𝑪𝑳𝑲𝑶𝑫𝑰𝑽 > 𝟎)
PS034404-0417
PRELIMINARY
44