Z32F0641MCU Datasheet, PDF (104/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Functional Description
16-Bit Timer
Timer Basic Operation
In Figure 11.2, TMCLK is a reference clock for operation of the timer. When this clock is divided by the
prescaler setting, the counting clock will work.
(a) Timer initialization is performed by the TCLR command and the timer is started by the TEN command.
(b) Timer is reset by matching GRB timing and counting again from 00.
Figure 11.2. Basic Start and Match Operation
The period of timer count can be calculated as shown in the following equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If the Tn.CR1.UAO bit is “0”, the Tn.CR2.TCLR command will initialize all the registers in the timer block and
load the GRA and GRB values into the Data0 and Data1 buffer. When you change the timer setting and
restart the timer with the new setting, it is recommended that you write the CR2.TCLR command before the
CR2.TEN command.
PS034404-0417
PRELIMINARY
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