Z32F0641MCU Datasheet, PDF (89/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Direct Memory Access Controller
DCn.PAR DMA Controller Peripheral Address Register
This register represents the peripheral addresses.
DC0.PAR=0x4000_0408 , DC1.PAR=0x4000_0418
DC2.PAR=0x4000_0428 , DC3.PAR=0x4000_0438
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Peripheral BASE OFFSET
PAR
0x4000
RO
0x0000
RW
31 PAR
0
Target Peripheral address of transmit buffer or receive
buffer.
User must set exact target peripheral buffer address in
this field.
If DIR is “0” this address is destination address of
data transfer.
If DIR is “1”, this address is source address of data
transfer.
DCn.MAR DMA Controller Memory Address Register
This register represents the memory addresses.
DC0.MAR=0x4000_040C , DC1.MAR=0x4000_041C
DC2.MAR=0x4000_042C , DC3.MAR=0x4000_043C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
0x2000
RO
0x0000
RW
31 MAR
0
Target memory address of data transfer.
Address is automatically incremented according to SIZE
bits when each transfer is done.
If DIR is “0” this address is source address of data tra
nsfer.
If DIR is “1”, this address is destination address of dat
a transfer.
PS034404-0417
PRELIMINARY
86