Z32F0641MCU Datasheet, PDF (105/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
16-Bit Timer
The update timing of the Data0 and Data1 buffer in dynamic operation is different in each operating mode and
depends on the Tn.CR1.UAO bit.
Normal Periodic Mode
Figure 11.3 shows the timing diagram in normal periodic mode. Tn.GRB value decides the timer period. One
more compare point is provided with Tn.GRA register value.
Figure 11.3. Normal Periodic Mode Operation
The period of timer count can be calculated as shown in the following equation:
The period = TMCLK Period * Tn.GRB value
Match A interrupt time = TMCLK Period * Tn.GRA value
If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”.
The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffers 0 and 1 when the loading
condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB
match event will load the compare data buffers.
When TnCR1.UAO is 1, the internal compare data buffer is updated whenever the Tn.GRA or Tn.GRB data is
updated.
The TnIO output signal will be toggled at every Match A condition time. If the value of TnGRA is 0, the TnIO
output does not change its previous level. If TnGRA is the same as TnGRB, the TnIO ouput will toggle at
same time as the counter start time. The initial level of the TnIO signal is decided by the TnCR1.STARTLVL
value.
One Shot Mode
Figure 11.4 shows the timing diagram in one shot mode. Tn.GRB value decides the one shot period. One
more compare point is provided with Tn.GRA register value.
PS034404-0417
PRELIMINARY
102