Z32F0641MCU Datasheet, PDF (164/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
MP0.DWL MPWM Duty WL Register
The PWM W channel duty register is a 16-bit register.
15
14
13
12
11
10
9
8
7
6
5
DUTY WL
0x0001
RW
Motor Pulse Width Modulator
MP0.DWL=0x4000_4024
4
3
2
1
0
15
DUTY WL
0
16-bit PWM Duty for WL output.
It should be larger than 0x0001
(if Duty is 0x0000, PWM will not work)
MP0.IER MPWM Interrupt Enable Register
The PWM Interrupt Enable Register is an 8-bit register.
7
PRDIEN
0
RW
6
BOTIEN
0
RW
5
WHIE
0
RW
4
VHIE
0
RW
3
UHIE
0
RW
2
WLIE
0
RW
MP0.IER=0x4000_4034
1
0
VLIE
ULIE
0
0
RW
RW
7
PRDIEN
6
BOTIEN
5
WHIE
ATR6IE
4
VHIE
ATR5IE
3
UHIE
ATR4IE
2
WLIE
ATR3IE
1
VLIE
ATR2IE
0
ULIE
ATR1IE
PWM Counter Period Interrupt enable
0 interrupt disable
1 interrupt enable
PWM Counter Bottom Interrupt enable
0 interrupt disable
1 interrupt enable
WH Duty or ATR6 Match Interrupt enable
0 interrupt disable
1 interrupt enable
VH Duty or ATR5 Match Interrupt enable
0 interrupt disable
1 interrupt enable
UH Duty or ATR4 Match Interrupt enable
0 interrupt disable
1 interrupt enable
WL Duty or ATR3 Match Interrupt enable
0 interrupt disable
1 interrupt enable
VL Duty or ATR2 Match Interrupt enable
0 interrupt disable
1 interrupt enable
UL Duty or ATR1 Match Interrupt enable
0 interrupt disable
1 interrupt enable
PS034404-0417
PRELIMINARY
161