Z32F0641MCU Datasheet, PDF (120/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Un.LSR UART Line Status Register
The UART Line Status Register is an 8-bit register.
7
6
5
4
3
-
TEMT
THRE
BI
FE
0
1
1
0
0
R
R
R
R
UART
U0.LSR=0x4000_8014, U1.LSR=0x4000_8114
2
1
0
PE
OE
DR
0
0
0
R
R
R
6
TEMT
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
Transmit empty.
0 Transmit register has the data is now transferring
1 Transmit register is empty.
Transmit holding empty.
0 Transmit holding register is not empty.
1 Transmit holding register empty
Break condition indication bit
0 Normal status
1 Break condition is detected
Frame Error.
0 No framing error.
1 Framing error. No valid stop bit in receive charact
ert
Parity Error
0 No parity error
1 Parity error. The receive character does not have
correct parity information.
Overrun error
0 No overrun error
1 Overrun error. Additional data arrives when the R
HR is full
Data received
0 No data in receive holding register.
1 Data received and saved in receive holding registe
r
This register provides the status of data transfers between the transmitter and receiver. Users can get the line
status information from this register and handle the next process. Bits 1,2,3, and 4 will cause the line status
Interrupt when RLSIE bit in UnIEN register is set. Other bits generate an interrupt when their interrupt enable
bit in UnIEN register is set.
PS034404-0417
PRELIMINARY
117