Z32F0641MCU Datasheet, PDF (37/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PRER2
Peripheral Reset Enable Register 2
The reset of each peripheral by Event Reset can be masked by this user setting. The PRER1/PRER2 register
controls enablement of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit
accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current
operation.
PRER2=0x4000_0024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000001100010000001100010001
21 ADC1
20 ADC0
16 MPWM0
9
UART1
8
UART0
4
I2C0
0
SPI0
ADC1 reset enable
ADC0 reset enable
MPWM0 reset enable
UART1 reset enable
UART0 reset enable
I²C0 reset enable
SPI0 reset enable
PS034404-0417
PRELIMINARY
34