Z32F0641MCU Datasheet, PDF (169/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

MP0.ATRm
MP0.ATR1
MP0.ATR2
MP0.ATR3
MP0.ATR4
MP0.ATR5
MP0.ATR6
Z32F0641 Product Specification
Motor Pulse Width Modulator
MPWMn ADC Trigger Counter m Register
MPWM ADC Trigger Counter 1 Register
MPWM ADC Trigger Counter 2 Register
MPWM ADC Trigger Counter 3 Register
MPWM ADC Trigger Counter 4 Register
MPWM ADC Trigger Counter 5 Register
MPWM ADC Trigger Counter 6 Register
The PWM ADC Trigger Counter register is a 32-bit register.
MP0.ATR1=0x4000_4058
MP0.ATR2=0x4000_405C
MP0.ATR3=0x4000_4060
MP0.ATR4=0x4000_4064
MP0.ATR5=0x4000_4068
MP0.ATR6=0x4000_406C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATCNT
000000000000 0 0 0
0x0000
RW
19 ATUDT
17 ATMOD
16
15 ATCNT
0
Trigger register update mode
0 ADC trigger value applied at period match event
(at the same time with period and duty registers update)
1 Trigger register update mode
When this bit set, written Trigger register values are sent
to trigger compare block after two PWM clocks (through
synchronization logic)
ADC trigger Mode register
00 ADC trigger Disable
01 Trigger out when up count match
10 Trigger out when down count match
00 Trigger out when up-down count match
ADC Trigger counter
(it should be less than PWM period)
PS034404-0417
PRELIMINARY
166