Z32F0641MCU Datasheet, PDF (117/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
UART
The UART supports 3-priority interrupt generation. The Interrupt Source ID register shows one interrupt
source which has the highest priority among pending interrupts. This priority is defined in the following order:
 Receive line status interrupt
 Receive data ready interrupt/Character timeout interrupt
 Transmit hold register empty interrupt
 Tx/Rx DMA complete interrupt
Priority
-
1
2
3
4
5
6
7
Table 12.4 Interrupt ID and Control
TXE
IID
IPEN
Interrupt Sources
Bit4 Bit3 Bit2 Bit1 Bit0 Interrupt
Interrupt
Condition
Interrupt Clear
0
0
0
0
1
None
-
-
Receiver
0
0
1
1
0
Line Status
Overrun, Parity,
Framing or
Break Error
Read LSR
register
0
0
1
0
0
Receiver
Data Available
Receive data
is available.
Read receive
register or read
IIR register
Transmitter
0
0
0
1
0
Holding
Register
Empty
Transmit
buffer empty
Write transmit
hold register
or read IIR
register
Write transmit
1
X
X
X
X
Transmitter
Register Empty
Transmit
registerr empty
hold register
or read IIR
register
0
1
1
0
0
Rx DMA done
Rx DMA
completed.
Read IIR
register
0
1
0
1
0
Tx DMA done
Tx DMA
completed.
Read IIR
register
Transmitter
Transmitter
1
X
X
X
X
register Empty
and DMA
regiser Empty Read IIR
and Tx DMA
register
done
completed.
PS034404-0417
PRELIMINARY
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