Z32F0641MCU Datasheet, PDF (134/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Functional Description
Serial Peripheral Interface
The SPI Transmit block and Receive block share the Clock Gen Block; however, they are independent of
each other. The Transmit and Receive blocks contain double buffers and SPI is available for back to back
transfer operation.
SPI Timing
The SPI has four modes of operation. These modes essentially control the way data is clocked in or out of an
SPI device. The configuration is done by two bits in the SPI control register (SPnCR). The clock polarity is
specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA)
control bit selects one of the two fundamentally different transfer formats. To ensure proper communication
between master and slave, both devices must run in the same mode. This may require a reconfiguration of
the master to match the requirements of different peripheral slaves.
The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to
be inverted (active high becomes active low and idle low becomes idle high). The settings of the clock phase,
however, select one of the two different transfer timings, which are described in detail in the following two
chapters. Because the MOSI and MISO lines of the master and the slave are directly connected to each other,
the diagrams show the timing of both devices. The nSS line is the slave select input of the slave. The nSS pin
of the master is not shown in the diagrams. It has to be inactive by a high level on this pin (if configured as
input pin) or by configuring it as an output pin.
The timing of a SPI transfer where CPHA is zero is shown in Figure 13.3 and Figure 13.4.
Two wave forms are shown for the SCK signal: one for CPOL equals zero and another for CPOL equals one.
When the SPI is configured as a slave, the transmission starts with the falling edge of the /SS line. This
activates the SPI of the slave and the MSB of the byte stored in its data register (SPnTDR) is output on the
MISO line. The actual transfer is started by a software write to the SPnTDR of the master. This causes the
clock signal to be generated. In cases where the CPHA equals zero, the SCLK signal remains zero for the first
half of the first SCLK cycle. This ensures that the data is stable on the input lines of both the master and the
slave. The data on the input lines is read with the edge of the SCLK line from its inactive to its active. The
edge of the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if
CPOL equals one) causes the data to be shifted one bit further so that the next bit is output on the MOSI and
MISO lines.
SCK
MOSI
MISO
D0
D1 D2
D3 D4 _D5
D6
D7
D0
D1 D2
D3 D4 _D5
D6
D7
Figure 13.3 Transfer Timing 1/4 (CPHA=0, CPOL=0, MSBF=0)
PS034404-0417
PRELIMINARY
131