Z32F0641MCU Datasheet, PDF (110/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
16-Bit Timer
Figure 11.8. Capture Mode Operation
A 5 PCLK clock cycle is required internally. Therefore, the actual capture point is after 5 PCLK clock cycles
from the rising or falling edge of the TnIO input signal.
The internal counter can be cleared in multiple modes. The TnCR1.CLRMD field controls the counter clear
mode. The following clear modes are supported: Rising edge, Falling edge, Both edges, and None.
The example in Figure 11.8 is of Rising edge clear mode.
ADC Trigger Function
The timer module can generate ADC start trigger signals. One timer can be one trigger source of the ADC
block. Trigger source control is performed by the ADC control register.
Figure 11.9 shows the ADC trigger function.
The conversion rate must be shorter than the timer period, else an overrun situation can occur. ADC
acknowledge is not required because the trigger signal is automatically cleared after 3 PCLK clock pulses.
PS034404-0417
PRELIMINARY
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