Z32F0641MCU Datasheet, PDF (25/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
FM.CFG.WAIT
000
001
010
011
Table 4.2. Flash Wait Control Recommendation
FLASH Access Wait
0 clock wait
Available Max System Clock Frequency
~16MHz
1 clock wait
~32MHz
2 clock wait
~48MHz
3 clock wait
~48MHz
Reset
The Z32F0641 MCU has two system resets:
 Cold reset by POR, which is effective during power up or down sequence, and
 Warm reset, which is generated by several reset sources. The reset event causes the chip to
return to initial state.
The cold reset has only one reset source, POR. The warm reset has the following reset sources:
 nRESET pin
 WDT reset
 LVD reset
 MCLK Fail reset
 MOSC Fail reset
 S/W reset
 CPU request reset
Cold Reset
Cold reset is an important feature of the chip when power is up. This characteristic globally affects the system
boot. Internal VDC is enabled when VDD power is turned on. The internal VDD level slope is followed by the
external VDD power slope. The internal PoR trigger level is 1.4 V of internal VDC voltage out level. At this
time, boot operation is started. The RINGOSC clock is enabled and counts to 4 msec for internal VDC level
stabilizing. During this time, the external VDD voltage level should be greater than the initial LVD level (2.3 V).
After counting 4 msec, the CPU reset is released and the operation is started.
Figure 4.6 shows the power up sequence and internal reset waveform.
PS034404-0417
PRELIMINARY
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