Z32F0641MCU Datasheet, PDF (129/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
SP0.RDR SPI Receive Data Register
SP0.RDR is a 17-bit read/write register. It contains serial receive data.
Serial Peripheral Interface
SP0.RDR=0x4000_9000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
000000000000000
0x00000
RW
16 RDR
0
Receive Data Register
SP0.CR
SPI Control Register
SP0.CR is a 20-bit read/write register which can be set to configure SPI operation mode.
SP0.CR=0x4000_9004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 00
20 TXBC
19 RXBC
18 TXDIE
17 RXDIE
16 SSCIE
15 TXIE
14 RXIE
13 SSMOD
Tx buffer clear bit.
0 No action
1 Clear Tx buffer
Rx buffer clear bit
0 No action
1 Clear Rx buffer
DMA Tx Done Interrupt Enable bit.
0 DMA Tx Done Interrupt is disabled.
1 DMA Tx Done Interrupt is enabled.
DMA Rx Done Interrupt Enable bit.
0 DMA Rx Done Interrupt is disabled.
1 DMA Rx Done Interrupt is enabled.
SS Edge Change Interrupt Enable bit.
0 nSS interrupt is disabled.
1 nSS interrupt is enabled for both edges (LH, HL)
Transmit Interrupt Enable bit.
0 Transmit Interrupt is disabled.
1 Transmit Interrupt is enabled.
Receive Interrupt Enable bit..
0 Receive Interrupt is disabled.
1 Receive Interrupt is enabled.
SS Auto/Manual output select bit.
PS034404-0417
PRELIMINARY
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