Z32F0641MCU Datasheet, PDF(26/205 Page) Zilog, Inc. – High Performance low-power Cortex-M3 core

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Z32F0641MCU Datasheet, PDF (26/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

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Z32F0641 Product Specification

System Control Unit

Figure 4.6. Power-up POR Sequence

The RSSR register shows the POR reset status. The last reset comes from POR; RSSR.PORST is set to â1â.

After power up, this bit is always â1â. If an abnormal internal voltage drop occurs during normal operation, the

system will be reset and this bit is also set to â1â.

When cold reset is applied, the chip returns to its initial state.

Warm Reset

The warm reset event has several reset sources. Some parts of the chip return to initial state when a warm

reset condition occurs.

The warm reset source is controlled by the RSER register and the status appears in the RSSR register. The

reset for each peripheral block is controlled by the PRER register. The reset can be masked independently.

PS034404-0417

PRELIMINARY

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