Z32F0641MCU Datasheet, PDF (88/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Direct Memory Access Controller
A DMA channel is connected to the selected peripheral. Table 9.3 shows the peripheral selections. This
PERISEL field must be configured with the correct number of peripherals that will be connected to the DMA
interface.
Table 9.3 DMAC PERISEL Selection
PERISEL[3:0]
Associatec Peipheral
0
CHANNEL IDLE
1
UART0 RX
2
UART0 TX
3
UART1 RX
4
UART1 TX
5
SPI0 RX
6
SPI0 TX
7
ADC0 RX
8
ADC1 RX
9 - 15
N.A.
Note: PERISEL cannot have the same value in different channels. If the same PERISEL value is wriiten in
more than one channel, proper operation is not guaranteed. Unused channels must contain CHANNEL IDLE
value in PERISEL bit postions.
DCn.SR DMA Controller Status Register
The DMA Controller Status Register is an 8-bit register. This register represents the current status of the DMA
Controller and enables DMA function.
DC0.SR=0x4000_0404 , DC1.SR=0x4000_0414
DC2.SR=0x4000_0424 , DC3.SR=0x4000_0434
7
6
5
4
3
2
1
0
EOT
DMAEN
1
0
0
0
0
0
0
0
RO
RW
7
EOT
0
DMAEN
End of transfer.
0 Data to be transferred is existing.
TRANSCNT shows non zero value
1 All data is transferred.
TRANSCNT shows now 0
DMA Enable
0 DMA is in stop or hold state
1 DMA is running or enabled
PS034404-0417
PRELIMINARY
85