Z32F0641MCU Datasheet, PDF (53/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
DBCLK2 Debounce Clock Control Register 2
The Debounce Clock Control register 2 controls the debounce timing configuration for Port C and Port D.
DBCLK2=0x4000_00A0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000
000
RW
0x01
RW
26 PDDCSEL
24
23 PDDDIV
16
10 PCDCSEL
8
7
PCDDIV
0
00000
000
RW
0x01
RW
Debounce Clock for PORT D source select bit
0xx RING OSC 1Mhz
100 MCLK (bus clock)
101 Reserved
110 External Main OSC (XTAL)
111 Reserved
PORT D Debounce Clock N divider
Debounce Clock for PORT C source select bit
0xx RING OSC 1Mhz
100 MCLK (bus clock)
101 Reserved
110 External Main OSC (XTAL)
111 Reserved
PORT C Debounce Clock N divider
MCCR1 Miscellaneous Clock Control Register 1
The Miscellaneous Clock Control register 1 controls the configuration for the System Tick clocks.
MCCR1=0x4000_0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000000000000000000000
000
RW
10 STCSEL
8
7
STDIV
0
SYSTIC Clock source select bit
0xx RING OSC 1Mhz
100 MCLK (bus clock)
101 Reserved
110 External Main OSC (XTAL)
111 Reserved
SYSTIC Clock N divider
0x01
RW
PS034404-0417
PRELIMINARY
50