Z32F0641MCU Datasheet, PDF (158/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Motor Pulse Width Modulator
MP0.OLR MPWM Output Level Register
The PWM Port Mode register is a 16-bit register.
MP0.OLR=0x4000_4004
7
6
5
4
3
2
1
0
WHL
VHL
UHL
WLL
VLL
ULL
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
5
WHL
4
VHL
3
UHL
2
WLL
1
VLL
0
ULL
0
Default Level
1
Inverted Level
0
Default Level
1
Inverted Level
0
Default Level
1
Inverted Level
0
Default Level
1
Inverted Level
0
Default Level
1
Inverted Level
0
Default Level
1
Inverted Level
The normal level is defined in each operating mode as shown in Table 15.3.
PWM Output
WH
WL
VH
VL
UH
UL
Table 15.3. MPWM Register Map
Level
Default level
NORMAL mode
UP mode
UPDOWN mode
LOW
HIGH
Active level
Default level
HIGH
LOW
LOW
LOW
Active level
HIGH
HIGH
Default level
Active level
LOW
HIGH
HIGH
LOW
Default level
Active level
LOW
HIGH
LOW
HIGH
Default level
Active level
LOW
HIGH
HIGH
LOW
Default level
Active level
LOW
HIGH
LOW
HIGH
MOTOR mode
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
The polarity control block is shown in Figure 15.2. The example shown is for WH signal polarity control.
PS034404-0417
PRELIMINARY
155