Z32F0641MCU Datasheet, PDF (52/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
DBCLK1 Debounce Clock Control Register 1
The Debounce Clock Control register 1 controls the debounce timing configuration for Port A and Port B.
DBCLK1=0x4000_009C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000
000
RW
0x01
RW
26 PBDCSEL
24
23 PBDDIV
16
10 PADCSEL
8
7
PADDIV
0
00000
000
RW
0x01
RW
Debounce Clock for Port B source select bit
0xx RING OSC 1Mhz
100 MCLK (bus clock)
101 Reserved
110 External Main OSC (XTAL)
111 Reserved
PORT B Debounce Clock N divider
Debounce Clock for Port A source select bit
0xx RING OSC 1Mhz
100 MCLK (bus clock)
101 Reserved
110 External Main OSC (XTAL)
111 Reserved
PORT A Debounce Clock N divider
PS034404-0417
PRELIMINARY
49