Z32F0641MCU Datasheet, PDF (140/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
I2C Interface
ICn.DR I²C Data Register
ICn.DR is an 8-bit read/write register. It contains a byte of serial data to be transmitted or a byte which has
just been received.
IC0.DR=0x4000_A000
7
6
5
4
3
2
1
0
DR
0xFF
RW
7 DR
0
The most recently received data or data to be transmitted.
ICn.SR
I²C Status Register
ICn.SR is an 8-bit read/write register. It contains the status of I²C bus interface. Writing to the register clears
the status bits except for IMASTER.
IC0.SR=0x4000_A008
7
6
5
4
3
2
1
0
GCALL
TEND
STOP
SSEL
MLOST
BUSY
TMODE
RXACK
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
7 GCALL
6 TEND
5 STOP
4 SSEL
3 MLOST
2 BUSY
1 TMODE
0 RXACK
General call flag
0 General call is not detected.
1 General call detected or slave address (ID byte) was sent.
1 Byte transmission complete flag
0 The transmission is working or not completed.
1 The transmission is completed.
STOP flag
0 STOP is not detected.
1 STOP is detected.
Slave flag
0 Slave is not selected.
1 Slave is selected.
Mastership lost flag
0 Mastership is not lost.
1 Mastership is lost.
BUSY flag
0
I²C bus is in IDLE state.
1
I²C bus is busy.
Transmitter/Receiver mode flag
0 Receiver mode.
1 Transmitter mode.
Rx ACK flag
0 Rx ACK is not received.
1 Rx ACK is received.
PS034404-0417
PRELIMINARY
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