Z32F0641MCU Datasheet, PDF (36/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PRER1 Peripheral Reset Enable Register 1
The reset of each peripheral by Event Reset can be masked by this user setting. The PRER1/PRER2 register
controls enablement of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit
accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current
operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
PRER1=0x4000_0020
8 765 4 3 2 1 0
0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 000 1 1 1 1 1
25 TIMER9
24 TIMER8
19 TIMER3
18 TIMER2
17 TIMER1
16 TIMER0
11 GPIOD
10 GPIOC
9
GPIOB
8
GPIOA
4
DMA
3
PCU
2
WDT
1
FMC
0
SCU
TIMER9 reset mask
TIMER8 reset mask
TIMER3 reset mask
TIMER2 reset mask
TIMER1 reset mask
TIMER0 reset mask
GPIOE reset mask
GPIOE reset mask
GPIOE reset mask
GPIOA reset mask
DMA reset mask
Port Control Unit reset mask
Watchdog Timer reset mask
Flash memory controller reset mask
System Control Unit reset mask
PS034404-0417
PRELIMINARY
33