Z32F0641MCU Datasheet, PDF (148/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
I2C Interface
Acknowledge
Data transfer with acknowledgement is obligatory. The acknowledge-related clock pulse is generated by the
master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.
The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable “L”
during the “H” period of this clock pulse; see Figure 14.9. Set-up and hold times must also be taken into
account.
When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because
it’s performing some real-time function), the data line must be left “H” by the slave. The master can then
generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If a slave-receiver acknowledges the slave address but cannot receive any more data bytes later during the
transfer, the master must again abort the transfer. This is indicated by the slave generating the not-
acknowledge on the first byte to follow. The slave leaves the data line “H” and the master generates a STOP
or a repeated START condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not
generating acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release
the data line to allow the master to generate a STOP or repeated START condition.
Data Output
By Transmitter
Data Output
By Receiver
SCL
MASTER
From
1
2
NAC
K
AC
K
8
9
Clock pulse for
ACK
Figure 14.9 I²C Bus Acknowledgement
PS034404-0417
PRELIMINARY
145