Z32F0641MCU Datasheet, PDF (48/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PLLCON PLL Control Register
Integrated PLL can synthesize the high speed clock for extremely high performance of the CPU from either
the internal oscillator (IOSC) or the external oscillator (MOSC). The PLL Control register provides the
configuration for the PLL system. By default, the PLL system is in reset mode and disabled. You must negate
the reset and enable the PLL to operate (bits 14 and 15 must be set). The Bypass bit must be set to output
the PLL clock. The active clock is defined in SCCR bit 2 (FIN).
To calculate the PLL output:
PLL Out = ((Active clock / PREDIV) * FBCTRL) / POSTDIV
For example:
Using MOSC (assuming it is running at 8 MHz and selected):
PREDIV set to 1
(FIN / 2)
FBCTRL set to 0x04
(M=12)
POSTDIV set to 0x00
(N=1)
((8 MHz / 2) * 12) = 48 MHz
PLLCON=0x4000_0060
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RW RW RW
R
RW
0000
RW
0000
RW
15 PLLRSTB
14 PLLEN
13 BYPASS
12 LOCK
8
PREDIV
7
FBCTRL
4
3
POSTDIV
0
PLL reset
0 PLL reset is asserted
1 PLL reset is negated
PLL enable
0 PLL is disabled
1 PLL is enabled
FIN bypass
0 FOUT is bypassed as FIN
1 FOUT is PLL output
LOCK status
0 PLL is not locked
1 PLL is locked
FIN predivider
0 FIN divided by 1
1 FIN divided by 2
Feedback control
0000 M = 4
1000
0001 M = 6
1001
0010 M = 8
1010
0011 M = 10
1011
0100 M = 12
1100
0101 M = 14
1101
0110 M = 16
1110
0111 M = 18
1111
Post divider control
000 N = 1
001 N = 2
010 N = 3
M = 20
M = 24
M = 26
M = 34
Not available
PS034404-0417
PRELIMINARY
45