Z32F0641MCU Datasheet, PDF (166/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Motor Pulse Width Modulator
MP0.SR[5:0] status bits are shared by the duty match interrupt event and the ADC trigger match interrupt
event. When ADC trigger mode is disabled, the interrupt is generated by the duty match condition. In other
cases, the interrupt is generated by the ADC trigger counter match condition. The ADC trigger mode is
selected by the ATMOD bit field in the ATRm register.
MP0.CNT MPWM Counter Register
The PWM Counter register is a 16-bit Read-Only register.
MP0.CNT=0x4000_4038
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT
0x0000
RW
CNT
PWM Counter Value
MP0.DTR MPWM Dead Time Register
The PWM Dead Time register is a 16-bit register.
MP0.DTR=0x4000_403C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0x00
RW
RW
RW
15 DTEN
14 PSHRT
8
DTCLK
7
DT
0
Dead-time function enable
2-channel symmetric mode does not support dead time
function. It should be disabled in 2 channel symmetric mode.
0 Disable Dead-time function
1 Enable Dead-time function
Protect short condition
This function is effective only for 2 channel symmetric mode.
For 1 channel mode, never activated on both H-side and L-
side at same time. L-side is always opposite of H-side.
0 Enable output short protection function.
(Turn off both output when both H-side and L-side are
1 ^active.)
Disable output short protection function.
Dead-time prescaler
0 Dead time counter uses PWM CLK/4
1 Dead time counter uses PWM CLK/16
Dead Time value (Dead time setting makes output delay of
‘low to high transition’ in normal polarity)
0x01 ~0xFF : Dead time
PS034404-0417
PRELIMINARY
163