Z32F0641MCU Datasheet, PDF (188/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
ADn.CCR ADCn Clock Control Register
ADC Control Registers are 16-bit registers.
12-Bit A/D Converter
15
14
13
12
11
10
9
8
7
AD0.CCR1=0x4000_B008, AD1.CCR1=0x4000_B108
6
5
4
3
2
1
0
CLKDIV
0
0x00
1
0
0
RW
RW
RW RW RW
15
ADCPDA
14
CLKDIV
8
7
ADCPD
6
EXTCLK
5
CLKINVT
ADC R-DAC disable to save power
Don’t set “1” here(it’s optional bit)
ADC clock divider when EXTCLK is ‘0’.
ADC clock = system clock/CLKDIV
CKDIV=0 : ADC clock=system clock
CKDIV=1 : ADC clock=stop
ADC Power Down
0 – ADC normal mode
1 – ADC Power Down mode
Select if ADC uses external clock.
0 – internal clock(CKDIV enabled)
1 – external clock(SCU clock)
Divided clock inversion(optional bit)
0 – duty ratio of divided clock is larger than 50%
1 – duty ratio of divided clock is less than 50%
PS034404-0417
PRELIMINARY
185