Z32F0641MCU Datasheet, PDF (124/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Functional Description
UART
General Operation
The UART module is compatible with 16450 UART. Additionally, dedicated DMA channels and fractional baud
rate compensation logic are provided. This UART module does not have an internal FIFO block. Therefore,
data transfers are established either interactively or with DMA support. The DMA operation is described in this
section.
Two DMA channels are provided for each UART module – one channel is for TX transfer and the other one is
for RX transfer. Each channel has a 32-bit memory address register and a 16-bit transfer counter register.
Prior to DMA operation, the DMA Memory Address Register and the Transfer Count Register should be
configured. For the RX operation, the memory address is the destination memory address and for the TX
operation, the memory address is the source memory address.
The transfer counter register stores the number count of transfer data. Each time a single transfer is done, the
counter is decremented by 1. When the counter reaches zero, the DMA done flag is delivered to the UART
control block. If the interrupt is enabled, this flag generates the interrupt.
Receiver Sampling Timing
The UARTs operates with the following timing.
If the falling edge is on the receive line, the UART determines it to be the start bit. From the start timing, UART
oversamples 16 times of 1-bit and detects the bit value at the 7th sample of 16 samples.
START bit
STOP bit
UnRXD
0
10
0
0
0
0
1
0
Bit Samples
Start bit Bit 0 Bit 1 _{Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7} Stop bit
UnRXD
SubSample
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bit Sampling Position (7/16)
Figure 12.2. Sampling Timing of UART Receiver
Note: Enable the debounce settings in the PCU block to reinforce the immunity of external glitch noise.
PS034404-0417
PRELIMINARY
121