Z32F0641MCU Datasheet, PDF (43/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
SCCR
System Clock Control Register
The Z32F0641 MCU has multiple clock sources to generate internal operating clocks. Each clock source can
be controlled by the System Clock Control Register. The MOSC MUST be running and stable before setting
the FINSEL bit.
SCCR=0x4000_0044
7
6
5
4
3
2
1
0
-
FINSEL
MCLKSEL
0000
R
0
00
RW
RW
2
FINSEL
1
MCLKSEL
0
PLL input source FIN select register
0 IOSC clock is used as FIN clock
1 MOSC clock is used as FIN clock
System clock select register
0 Internal sub oscillator
X
10 PLL bypassed clock
11 PLL output clock
Note: When changing FINSEL, both internal OSC and external OSC should be alive to prevent the chip from
mal functioning.
PS034404-0417
PRELIMINARY
40