Z32F0641MCU Datasheet, PDF (191/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
12-Bit A/D Converter
ADn.CR ADCn Control Register
The ADCn Control Register controls start or stop ADC conversion operations. This register is an 8-bit register.
AD0.CR=0x4000_B020, AD1.CR=0x4000_B120
7
6
5
4
3
2
1
0
ASTOP
ASTART
0
0
W
RW
7
ASTOP
0
ASTART
0 No
1 ADC conversion stop (will be clear next @ADC clock)
If ASTOP set after conversion cycle start, present
conversion would be completed.
0 No ADC conversion
1 ADC conversion start (will be clear next @ADC clock)
ADCEN should be “1” to start ADC
If ASTART is set as 1’h1 when ARST is 1’h0 in trigger
event mode, ADC conversion will start once as
SEQCNT set.
ADn.SR ADCn Status Register
The ADC Status Register is a 32-bit register.
7
EOC
0
RO
6
ABUSY
0
RO
5
DOVRUN
0
RO
4
DMAIRQ
0
RO
7
EOC
6
ABUSY
5
DOVRUN
4
DMAIRQ
3
TRGIRQ
2
EOSIRQ
0
EOCIRQ
3
TRGIRQ
0
RC
AD0.SR=0x4000_B024, AD1.SR=0x4000_B124
2
1
0
EOSIRQ
-
EOCIRQ
0
-
0
RC
-
RC
ADC End-of-Conversion flag
(Start-of-Conversion made by ADC_CLK clears this
bit , not ASTART)
ADC conversion busy flag
DMA overrun flag (not interrupt)
(DMA ACK didn’t come until end of next conversion)
DMA done received (DMA transfer is completed)
ADC Trigger interrupt flag(Write “1” to clear flag)
(0: no int / 1: int occurred)
This flag will be set upon final end of a sequence
(Write “1” to clear flag)
0 None.
1 End-of-Sequence(burst) Interrupt occurred
This flag will be set upon each conversion when a
sequence occurs. Use this bit when polling the ADC
for completion in single conversion mode. (Write “1”
to clear flag)
0 None.
1 End-of-Conversion Interrupt occurred
PS034404-0417
PRELIMINARY
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