Z32F0641MCU Datasheet, PDF (34/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
RSER Reset Source Enable Register
The reset source to the CPU is selected by the Reset Source Enable Register. When 1 is written in the bit
field of each reset source, the reset source event is transferred to the reset generator. When 0 is written in the
bit field of each reset source, the reset source event is masked and does not generate a reset event.
RSER=0x4000_0018
7
6
5
4
3
2
1
0
PINRST
CORERST
SWRST
WDTRST
MCKFRST
XFRST
LVDRST
0
1
0
0
1
0
0
1
RW
RW
RW
RW
RW
RW
RW
6
PINRST
5
CPURST
4
SWRST
3
WDTRST
2
MCKFRST
1
XFRST
0
LVDRST
External pin reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
CPU request reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
Software reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
Watchdog Timer reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
MCLK Clock fail reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
External OSC Clock fail reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
LVD reset enable bit
0 Reset from this event is masked
1 Reset from this event is enabled
PS034404-0417
PRELIMINARY
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