Z32F0641MCU Datasheet, PDF (130/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

12 SSOUT
11 LBE
10 SSMASK
9 SSMO
8 SSPOL
7
6
5 MS
4 MSBF
3 CPHA
2 CPOL
1 BITSZ
0
Z32F0641 Product Specification
Serial Peripheral Interface
0 SS output is not set by SSOUT (SPnCR[12]).
- SS signal is in normal operation mode.
1 SS output signal is set by SSOUT.
SS output signal select bit.
0 SS output is ‘L.’
1 SS output is ‘H’.
Loop-back mode select bit in master mode.
0 Loop-back mode is disabled.
1 Loop-back mode is enabled.
SS signal masking bit in slave mode.
0 SS signal masking is disabled.
- Receive data when SS signal is active.
1 SS signal masking is enabled.
- Receive data at SCLK edges. SS signal is ignored.
SS output signal select bit.
0 SS output signal is disabled.
1 SS output signal is enabled.
SS signal Polarity select bit.
0 SS signal is Active-Low.
1 SS signal is Active-High.
Reserved
Master/Slave select bit.
0 SPI is in Slave mode.
1 SPI is in Master mode.
MSB/LSB Transmit select bit.
0 LSB is transferred first.
1 MSB is transferred first.
SPI Clock Phase bit.
0 Sampling of data occurs at odd edges (1,3,5,…,15).
1 Sampling of data occurs at even edges (2,4,6,…,16).
SPI Clock Polarity bit.
0 Active-high clocks selected.
1 Active-low clocks selected.
Transmit/Receive Data Bits select bit.
00 8 bits
01 9 bits
10 16 bits
11 17 bits
CPOL=0, CPHA=0 : data sampling at rising edge, data changing at falling edge
CPOL=0, CPHA=1 : data sampling at falling edge, data changing at rising edge
CPOL=1, CPHA=0 : data sampling at falling edge, data changing at rising edge
CPOL=1, CPHA=1 : data sampling at rising edge, data changing at falling edge
PS034404-0417
PRELIMINARY
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