Z32F0641MCU Datasheet, PDF (84/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Figure 7.3 shows the page write operation.
Flash Memory Controller
Figure 7.3.Page Erase Timing Diagram
The Flash erase of page data is done by the ERS.FM.CR command. Safe writing operation requires correct
program time. The erase time tERS is defined by the FM.TMR register. This timer counts the number of HCLK
clock to the FM.TMR value. When the timer count starts, the IDLE.FM.MR register is cleared. When the timer
count is completed, the IDLE.FM.MR register is set.
Figure 7.4 shows the bulk erase operation.
Figure 7.4. Bulk Erase Timing Diagram
PS034404-0417
PRELIMINARY
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