Z32F0641MCU Datasheet, PDF (23/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
HCLK Clock Domain
The HCLK clock feeds the clock to the CPU and AHB bus. The Cortex-M3 CPU requires two clocks related
with the HCLK clock:
FCLK – FCLK is a free-running clock which runs continuously except during Power-Down Mode
HCLK – HCLK can be stopped during Idle Mode
Miscellaneous Clock Domain for Cortex-M3
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
0XX
100
1/N
SysTick CLK
110
SYSTICKDIV (MCCR1)
0XX
100
1/N
WDT CLK
110
WDTDIV (MCCR3)
WDTCSEL
0XX
100
1/N
TIMER CLK
110
TIMERDIV (MCCR3)
TIMERCSEL
0XX
100
1/N
MPWM0 C
110
LK
MPWM0DIV (MCCR2)
MPWMCSEL
0XX
100
1/N
ADC_CLK
110
ADCDIV (MCCR7)
ADCCSEL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
RingOSC
MCLK
XTAL
0XX
100
1/N
PA_DEBOUNCE
110
PADDIV (MCCR4)
PADCSEL
0XX
100
1/N
PB_DEBOUNCE
110
PBDDIV (MCCR4)
PBDCSEL
0XX
100
1/N
PC_DEBOUNCE
110
PCDDIV (MCCR5)
PCDCSEL
0XX
100
1/N
PD_DEBOUNCE
110
PDDDIV (MCCR5)
PDDCSEL
Figure 4.4 Miscellaneous Clock Configuration
PS034404-0417
PRELIMINARY
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