Z32F0641MCU Datasheet, PDF (21/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
4. System Control Unit
Overview
The Z32F0641 microcontroller has an in-built intelligent power control block which manages the system
analog blocks and operating modes. Internal reset and clock signals are controlled by the SCU block to
maintain optimal system performance and power dissipation.
APB BUS
RESET
INTERRUPT
INTERRUPT
SCU
MODE CONTROL
SCU
CLOCK GEN
SLEEP
WAKE UP
VDC/LVD/PLL
IntOSC CONTROL
SCU
HCLK
PCLK
Wakeup
Source
Figure 4.1 SCU Block Diagram
Clock System
The Z32F0641 MCU has the following two main operating clocks:
HCLK – Clock for the CPU and AHB bus system
PCLK – Clock for peripheral systems
Figure 4.2 and Figure 4.3 show the chip’s clock system. Table 4.1 lists the clock source descriptions.
PS034404-0417
PRELIMINARY
18