Z32F0641MCU Datasheet, PDF (173/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Motor Pulse Width Modulator
The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active
level when the H-side duty level is matched in up count period and is returned to the default level when the L-
side duty level is matched in down count period.
When the PSTART is set, the L-side PWM output is changed to the active level, then the L-side PWM output
is the inverse output of the H-side output.
Motor PWM 1-Channel Symmetric Mode Timing
The 1-channel symmetric mode generates a symmetric duration pulse which is defined by the H-side DUTY
register. Therefore, the L-side signal is always the negative signal of H-side. During up count period, the H-
side DUTY register matching condition generates the active level pulse and during down count period, the H-
side DUTY register matiching condition also generates the default level pulse.
Figure 15.8. 1-Channel Symmetric Mode Waveform (MOTORB=0,MCHMOD=10)
The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active
level when the H-side duty level is matched in up count period and is returned to the default level when the H-
side duty level is matched again in down count period.
When the PSTART is set, the L-side pwm output is changed to the active level, then the L-side PWM output is
the inverse output of H-side output.
PWM Dead-Time Operation
To prevent an external short condition, the MPWM provides a dead-time function. This function is only
available in the Motor PWM mode. When either theH-side or L-side output changes to active level, an amount
of dead-time is inserted if the DTEN.MP.DTR bit is enabled.
The duration of dead-time is decided by the value in the DT.MP.DTR[7:0] field.
When DTCLK = 0, the dead-time duration = DT[7:0] * (PWM clock period * 4)
When DTCLK = 1, the dead-time duration = DT[7:0] * (PWM clock period * 16)
When the PWM counter reaches the duty value, the PWM output is masked and the dead-time counter starts
to run. When the dead-time counter reaches the value in the DT[7:0] register, the output mask is disabled.
PS034404-0417
PRELIMINARY
170