SH7146 Datasheet, PDF(997/1022 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH7146 Datasheet, PDF (997/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Item

Page Revision (See Manual for Details)

Table 8.11 DTC Bus Release

Timing

190 Amended

Bus Function Extending Register (BSCEHR) Setting

Setting

DTLOCK CSSTP1 CSSTP2 CSSTP3 DTBST

Setting 1*4 1

0

*3

1

0

Setting 2*3 0

0

0

*3

0

Setting 3 0

1

*3

*3

0

Setting 4*2 0

1

*3

*3

1

Setting 5 1

1

*3

1

0

Notes: 1. The bus mastership is only released for the

external space access request from the CPU

after a vector read.

3. Don't care.

4. Set the CSSTP3 bit to 1 when selecting

setting 1.

8.9.11 Operation when a DTC 198 Added

Activation Request is Cancelled

While in Progress

9.1 Features

199 Amended

9.3.2 Address Map

â¢ A maximum 1 Mbyte for each of two areas, CS0 and

CS1

201 Amended

The external address space has a capacity of 2 Mbytes

and is used by dividing into two spaces.

Table 9.3 Address Map (SH7149 203

in On-Chip ROM-Enabled Mode)

Added and Amended

Address

Area

H'02000000 to CS0 space

H'020FFFFF

H'02100000 to Reserved

H'03FFFFFF

H'04000000 to CS1 space

H'040FFFFF

H'04100000 to Reserved

H'FFFF8FFF

Bus

Memory Type Capacity Width

Normal space 1 Mbyte 8 or 16

bits*

Normal space 1 Mbyte 8 or 16

bits*

Rev. 3.00 May 17, 2007 Page 953 of 974

REJ09B0229-0300

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