SH7146 Datasheet, PDF (76/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
Instruction Format
Destination
Source Operand Operand
Sample Instruction
d type
15
0
xxxx xxxx dddd dddd
d12 type
15
0
xxxx dddd dddd dddd
dddddddd: GBR
indirect with
displacement
R0 (register direct) MOV.L @(disp,GBR),R0
R0 (register direct) dddddddd: GBR
indirect with
displacement
MOV.L R0,@(disp,GBR)
dddddddd:
PC relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0

dddddddd:
BF label
PC relative

dddddddddddd: BRA label
PC relative
(label=disp+PC)
nd8 type
15
0
xxxx nnnn dddd dddd
dddddddd: PC
relative with
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
i type
15
0
xxxx xxxx iiii iiii
ni type
15
0
xxxx nnnn iiii iiii
iiiiiiii:
immediate
iiiiiiii:
immediate
iiiiiiii:
immediate
iiiiiiii:
immediate
Index GBR indirect AND.B #imm,@(R0,GBR)
R0 (register direct) AND #imm,R0

TRAPA #imm
nnnn: register
direct
ADD #imm,Rn
Note: * In multiply and accumulate instructions, nnnn is the source register.
Rev. 3.00 May 17, 2007 Page 32 of 974
REJ09B0229-0300