SH7146 Datasheet, PDF (482/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 10.121 shows the timing in this case.
MPφ
TCNT write cycle
T1 T2
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 10.121 Contention between TCNT Write and Increment Operations
Rev. 3.00 May 17, 2007 Page 438 of 974
REJ09B0229-0300