SH7146 Datasheet, PDF (576/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 Watchdog Timer (WDT)
13.5 Usage Note
13.5.1 WTCNT Setting Value
If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT changes
from H'FF to H'00 after one cycle of count clock, but overflow occurs when WTCNT changes
from H'FF to H'00 after 257 cycles of count clock.
If WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from
H'FF to H'00 after one cycle of count clock.
Rev. 3.00 May 17, 2007 Page 532 of 974
REJ09B0229-0300