SH7146 Datasheet, PDF (648/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 A/D Converter (ADC)
15.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2)
ADCSR for each module controls A/D conversion operations.
Bit: 15 14 13
ADF ADIE -
Initial value: 0
0
0
R/W:R/(W)* R/W R
12 11 10 9
8
7
6
5
4
3
2
1
0
- TRGE - CONADF STC
CKSL[1:0]
ADM[1:0] ADCS
CH[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit Bit Name Value
15
ADF
0
14
ADIE
0
13, 12 
All 0
11
TRGE
0
R/W
R/(W)*
R/W
R
R/W
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt and
ADDR is read
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG, an MTU2 trigger, or an MTU2S trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
When changing the operating mode, first clear the
ADST bit to 0.
Rev. 3.00 May 17, 2007 Page 604 of 974
REJ09B0229-0300