SH7146 Datasheet, PDF (249/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.4 Register Descriptions
The BSC has the following registers. Refer to section 23, List of Registers, for details on the
register addresses and register states in each operating mode.
Do not access spaces other than CS0 until the termination of the memory interface setting.
Table 9.5 Register Configuration
Register Name
Abbrevia-
tion
R/W Initial Value Address
Access Size
Common control register
CMNCR R/W H'00001010 H'FFFFF000 32
CS0 space bus control register CS0BCR R/W H'36DB0600 H'FFFFF004 32
CS1 space bus control register CS1BCR R/W H'36DB0600 H'FFFFF008 32
CS0 space wait control register CS0WCR R/W H'00000500 H'FFFFF028 32
CS1 space wait control register CS1WCR R/W H'00000500 H'FFFFF02C 32
Bus function extending register BSCEHR R/W H'0000
H'FFFFE89A 8, 16
9.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area.
Do not access external memory other than area 0 until the register initialization is complete.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- HIZMEM -
Initial value: 0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R
Rev. 3.00 May 17, 2007 Page 205 of 974
REJ09B0229-0300