SH7146 Datasheet, PDF (885/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 21 RAM
Section 21 RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus (L bus), and to the data transfer controller (DTC) by a 32-bit data bus (I bus),
enabling 8, 16, or 32-bit width access to data in the on-chip RAM.
The on-chip RAM is allocated to different addresses according to each product as shown in figure
21.1, and the on-chip RAM is divided into page 0 and page 1 based on the addresses. The on-chip
RAM can be accessed from the CPU (via the L bus) and DTC (via the I bus). When different
buses request to access the same page simultaneously, the priority becomes I bus (DTC) > L bus
(CPU). Since such kind of conflict degrades the RAM access performance, software should be
created so as to avoid conflicts. For example, conflict does not occur when the buses access
different pages. An access from the L bus (CPU) is a 1-cycle access as long as page conflict does
not occur. The number of bus cycles in accesses from the I bus (DTC) differ depending on the
ratio between the internal clock (Iφ) and bus clock (Bφ), and the operating state of the DTC. The
contents of the on-chip RAM are retained in sleep mode or software standby mode, and at a
power-on reset or manual reset. However, the contents of the on-chip RAM are not retained in
deep software standby mode.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control
register (RAMCR). For details on the RAM control register (RAMCR), refer to section 22.3.7,
RAM Control Register (RAMCR).
H'FFFF9000
H'FFFF9FFF
H'FFFFA000
H'FFFFAFFF
Page 0
4 kbytes
Page 1
4 kbytes
SH7146/SH7149
(8 kbytes)
Figure 21.1 On-chip RAM Addresses
RAM0200A_010020030800
Rev. 3.00 May 17, 2007 Page 841 of 974
REJ09B0229-0300