SH7146 Datasheet, PDF (245/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.2 Input/Output Pins
The pin configuration of the BSC is listed in table 9.1.
Table 9.1 Pin Configuration
Name
A19 to A0
D15 to D0
CS0 and CS1
RD
WRH
WRL
WAIT
BREQ
BACK
I/O
Function
Output Address bus
I/O
Data bus
Output Chip select
Output Read pulse signal (read data output enable signal)
Output Indicates byte write through D15 to D8.
Output Indicates byte write through D7 to D0.
Input External wait input
Input Bus request input
Output Bus acknowledge output
9.3 Area Overview
9.3.1 Area Division
In the architecture, this LSI has 32-bit address spaces.
As listed in tables 9.2 to 9.4, this LSI can connect two areas to each type of memory, and it
outputs chip select signals (CS0 and CS1) for each of them. CS0 is asserted during area 0 access.
9.3.2 Address Map
The external address space has a capacity of 2 Mbytes and is used by dividing into two spaces.
The memory to be connected and the data bus width are specified in each space. The address map
for the entire address space is listed in tables 9.2 to 9.4.
Rev. 3.00 May 17, 2007 Page 201 of 974
REJ09B0229-0300