SH7146 Datasheet, PDF (1000/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
10.3.5 Timer Interrupt Enable
Register (TIER)
• TIER_5
Page Revision (See Manual for Details)
281 Amended
Bit Bit Name Description
2 TGIE5U TGR Interrupt Enable 5U
Enables or disables interrupt requests (TGIU_5)
by the CMFU5 bit when the CMFU5 bit in TSR_5
is set to 1.
1 TGIE5V TGR Interrupt Enable 5V
Enables or disables interrupt requests (TGIV_5)
by the CMFV5 bit when the CMFV5 bit in TSR_5
is set to 1.
0 TGIE5W TGR Interrupt Enable 5W
Enables or disables interrupt requests (TGIW_5)
by the CMFW5 bit when the CMFW5 bit in
TSR_5 is set to 1.
10.3.23 Timer Gate Control
Register (TGCR)
Figure 10.41 Example of
Operation without Dead Time
317 Note added
Note: * When the MTU2S is used to set the BDC bit to
1, do not set the FB bit to 0.
370 Amended
TGRA_3=TCDR+1
TCDR
TGRA_4
TGRC_4
Ta
Tb1
TCNTS
TCNT_3
TCNT_4
TDDR=1
H'0000
Buffer register TGRC_4
Temporary register TEMP2
Compare register TGRA_4
Output waveform
Initial output
Output waveform
Initial output
Data1
Data1
Rev. 3.00 May 17, 2007 Page 956 of 974
REJ09B0229-0300