SH7146 Datasheet, PDF (273/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
• When DTC activation request is generated during read access to external space from CPU
Internal bus
Read access to external
space from CPU
DTC
External bus
DTC
activation request
Read access to external
space from CPU
DTC activation request is generated in this period.
• When DTC activation request is generated during write access to external space from CPU (1)
Internal bus
Write to external
space from CPU
DTC
External bus
DTC
activation request
Write access to external
space from CPU
DTC activation request is generated in this period.
• When DTC activation request is generated during write access to external space from CPU (2)
(When external space read request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external
space from CPU
Read access to external
space from CPU
DTC
External bus
DTC
activation request
Write access to external
space from CPU
Read access to external
space from CPU
DTC activation request is generated in this period.
• When DTC activation request is generated during write access to external space from CPU (3)
(When external space write request is generated by CPU during execution of write access to external space from CPU)
Internal bus
Write to external Write to external
space 1 from CPU space 2 from CPU
DTC
External bus
DTC
activation request
Write access to external
space 1 from CPU
Write access to external
space 2 from CPU
DTC activation request is generated in this period.
Figure 9.10 Bus Arbitration When DTC Activation Request Occur during External Space
Access from CPU
Rev. 3.00 May 17, 2007 Page 229 of 974
REJ09B0229-0300