SH7146 Datasheet, PDF (486/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 10.125 and 10.126 show the timing in this case.
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 10.125 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
M
Figure 10.126 Contention between TGR Read and Input Capture (Channel 5)
Rev. 3.00 May 17, 2007 Page 442 of 974
REJ09B0229-0300